As electronic devices and systems continue to evolve, their operating speeds continue to increase. However, some components of such devices and systems may operate at a lower speed, and therefore may not be compatible with, or may limit, high speed devices or systems. Because of the high data rates of many networking applications, it may be necessary to multiplex the input data words operating at a high frequency into a larger data word, comprised of several smaller data words, operating at a lower frequency.
One conventional networking standard which enables the development of interoperable products and services for data switching and routing using optical networking technologies provides an example in which this multiplexing must be done. In this networking standard, for example, the interface data bus is 16-bits wide and operates dual-data-rate (DDR) at up to 500 MHz. In order to internally process that data in a device operating at a lower speed, it is necessary to multiplex that data into an internal format of a wider parallel bus operating at a lower clock frequency (i.e. 64-bits at 250 MHz). Conversely, when writing data out, it is necessary convert the data from the internal parallel bus at the lower frequency to the external 16-bit dual-data-rate format at the higher frequency. In this standard, between one and nine 16-bit data words may be written into the memory per clock cycle. Because of the multiplexing necessary to send one 16-bit DDR word at 500 MHz, the internal logic must read four 16-bit words from memory per 250 MHz clock cycle.
However, there is not a straight conversion between the data buses. The received data contains headers that must be separated from the raw data payloads. After stripping headers, some number of data words are passed on to the user. Further, the data may be too much to place on the user bus at once. A conventional approach could be to predict the various combinations of input words that could occur, and create logic to assemble four or less output data words from these combinations. Although shift registers have been used to implement FIFOs, they normally only shift by +1. A large array of complex logic would be needed to create a FIFO to generate the fixed output data to enable the conversion between the data buses.
Accordingly, there is a need for an improved integrated circuit and method of outputting data from a FIFO which can operate at a lower clock rate and read or write data at a higher clock rate.